Logic device/transceiver/encoder

4-Channel, 2-Input, 1.65V to 3.6V OR Gate 14-TSSOP -40 to 125

The MC14042B quad transparent latch is constructed using MOS P-channel and N-channel enhancement mode devices in a monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latch can be preserved using the polarity input. The information presented at the data input is transferred to the outputs Q and Q during the clock level determined by the polarity of the input. When the polarity input is at a logic "0" state, data is transferred during the low period of the clock, and when the polarity input is at a logic "1" state, data is transferred during the high period of the clock.

16-Bit Transparent D-Type Latch with 3-State Output 48-SSOP -40 to 85

Octal Bus Transceiver with 3-State Outputs 20-PDIP -40 to 85