onsemi (Ansemi)
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MC100EP51DTR2G
ECL D-type flip-flop with reset input and differential clock
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Logic Devices > Flip Flops
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The MC10/100EP51 is a differential clocked D-type flip-flop with reset. The device is functionally identical to the EL51 and LVEL51 devices. The reset input is an asynchronous, level-triggered signal. Data enters the master portion of the flip-flop when the clock is low, then transfers to the slave portion, and thus transfers to the output on a positive transition of the clock. The EP51's differential clock input allows the device to be used as a falling-edge triggered flip-flop. The differential inputs employ clamping circuits to maintain stability under open-circuit input conditions. When left open, the CLK input will be pulled down to VEE and the CLKbar input will be biased at VCC / 2.
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재고 75685 PCS