Logic device/transceiver/encoder

2-Channel, 2-Input, 0.8V to 3.6V Low Power NAND Gate 8-UQFN -40 to 85

Single 1 Input, 1.65V to 5.5V NAND Gate 6-SON -40 to 125

The NB7VQ1006M is a high performance equalizer receiver (signal booster) operating at a maximum speed of 10 Gbps/7.5 GHz from a 1.8 V or 2.5 V supply. When placed in series in the data/clock path, the receiver will amplify the degraded signal traveling in the FR4 backplane or cable interconnect and output six identical CML copies of the input signal. An equalizer enable pin (EQEN) allows the IN/IN input to flow through or bypass the equalizer section. The equalizer function can be controlled by setting EQEN. When EQEN is set low, the IN/IN input bypasses the equalizer. When EQEN is set high, the IN/IN input flows through the equalizer. The default state at startup is low. The differential data/clock inputs are in a 100 Ω center-tapped configuration combined with a pair of internal 50 Ω termination resistors through the VT pin and accept LVPECL, CML, or LVDS logic levels. This feature provides on-chip transmission line termination at the receiver side, requiring no external components. The NB7VQ1006M is a member of the PEEQ GigaComm series of high-performance data/clock products.